The conventional parallel flash analog-to-digital (A/D) converter used to digitize video signals is shown in FIG. 5. The flash A/D converter produces 256 digital codes, words, corresponding to 256 equally spaced analog input voltages.
The conventional flash A/D converter 50 operates by comparing the input analog signal against a large number of linearly increasing reference voltage levels in parallel. A 8-bit flash A/D converter includes 255 distinct analog voltage comparators 20. An encoder 30 produces a digital signal ENC-OUT in response to one of the comparators 20(1)-20(255) with the highest reference voltage that is not less than the voltage level of a given input analog signal. The output produced by the comparators is provided to the input terminals I(0) to I(255) of the encoder 30.
The flash A/D converter 50 includes resistors 10(1) to 10(255) connected in series between a ground GND and a reference voltage VREF. Coupled between each pair of resistors is a comparator 20(1)-20(255) which is also coupled to an analog input signal AIN. The input terminals of comparators 20(1)14 20(255) are connected in parallel to the same analog input signal AIN so that the same analog voltage appears on the additive input terminal of each comparator. The subtractive input terminals of comparators 20(1) to 20(255) are coupled to respective reference voltage levels which are generated by resistors 10(1) to 10(255) connected in series.
Resistors 10(1) to 10(255) are ideally of equal value and, thus, for a given current, produce equally spaced reference voltages. That is to say, the reference voltages between ground GND and the respective subtractive input terminal of comparators 20(1)-20(255) increase in equal increments. Assuming the reference voltage at the subtractive input terminal of comparator 20(1) is A, for example, then the reference voltage at the subtractive input terminal of comparators 20(2) and 20(255) are 2 A and 255 A respectively.
The logic signals produced by comparators 20(1) to 20(255) are applied to input terminals I(1) to I(255). The comparator signals are used by the encoder 30 to produce one of 256 different digital codes which are provided to a latch 40 as an eight bit parallel digital signal. In response to a clock signal CLK, latch 40 provides a 8-bit digital signal DOUT.
The number of comparators 20 for the conventional parallel flash A/D converter 50 doubles with each increment in bit resolution so that building a very high resolution flash converter becomes unreasonable. For example, if the digital resolution is increased by a factor of two, then the number of comparators is increased to 511.
When the resolution of the A/D converter shown in FIG. 5 is increased, the sample points over the analog signal to be converted are desirably equally spaced. Thus, resolution is desirably increased uniformly. This occurs because the resistors 10(1)-10(255) have equal resistances and provide the same reference voltage drop across that resistance.
FIG. 6 illustrates the resolution of the conventional A/D converter. The digital codes are on the x-axis and the input analog signal scaled to 256 voltage levels are the y-axis.
There are times, however, when equally spaced sample points for the analog input voltages are not necessary. For example, CCD sensors may have more total noise at levels near white than at those near black and since the desired digital resolution is a function of the analog noise of the sample signal, coarser quantization may be tolerated near white (i.e., any quantization distortion in the signal is masked by the noise).
In addition to noise, video applications are increasingly requiring higher speeds for converting and processing images as, for example, is required for high definition television (HDTV). For example, as the speed of camera systems increase to provide video for HDTV, the power consumption of the camera systems increase. As a result, the power consumption of the camera system becomes a speed limiting factor for the camera systems. Accordingly, when the power consumption of the camera system can be reduced, higher speeds may be attained.
Coarser quantization can be performed by simply disregarding unneeded levels produced by A/D converter 50. Since there is no reduction in circuitry, this offers no advantage over the system which uses all available codes. In addition, the simple limitation does not produce advantages such as power dissipation and increased conversion speed.
An alternative A/D is shown in U.S. Pat. No. 5,066,952 entitled NON-LINEAR DATA CONVERSIONS SYSTEM FOR DYNAMIC RANGE DIGITAL SIGNAL PROCESSING issued to Koerner, which illustrates a method for performing non-linear conversion. In the '952 patent, the conventional A/D converter shown in FIG. 5 is modified to provide a proportionally larger number of comparators to accommodate high resolution requirements. The resistors 10(1)-10(255) are of graduated, unequal values. For example, the resistor values may be related as a geometric progression. As a result, the A/D conversion process provides a form of data compression which results in an A/D conversion that is non-linear. In the '952 patent an additional read only memory (ROM) is provided to decompress the digital data which has been compressed in the A/D converter. The A/D converter of the '952 patent does not reduce power consumption and actually increases the complexity of the system. This occurs because an additional component, the mapping read-only-memory, is required to convert the non-linear digital signal provided by the A/D converter to a linear digital signal. This extra component may also increase power dissipation.
Another conventional A/D is shown in U.S. Pat. No. 5,053,771, entitled ADAPTIVE DUAL RANGE ANALOG TO DIGITAL CONVERTER, issued to McDermott (hereinafter the '771 patent). The '771 discloses an adaptive dual range A/D converter which includes an input signal range selection device for selecting a segment of the input analog signal to be converted to digital form using fine resolution quantization. The '771 patent, however, uses two A/D converters to provide coarse resolution and fine resolution. The digital words produced by the coarse and fine A/D converters is provided to a multiplexer which, then, selects the outputs of the coarse and fine A/D converters. In this case, however, two A/D converters are provided as well as a multiplexer to perform the A/D conversion.
Accordingly, there is a need for an analog to digital converter which performs linear A/D conversion combined with non-linear resolution levels providing lower power dissipation for higher speed applications.